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Branch predictor
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51	Itanium™ Processor Core Intel® Itanium™ Processor Core Harsh Sharangpani Principal Engineer and IA-64 Microarchitecture Manager Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:38:11 Central processing unit Instruction set architectures Microprocessors Itanium CPU cache Processor register Microarchitecture Branch predictor Multi-core processor Computer architecture Computer hardware Computer engineering
52	Probabilistic Counter Updates for Predictor Hysteresis and Stratification Nicholas Riley Craig Zilles Department of Computer Science Add to Reading List Source URL: sabi.net Language: English - Date: 2005-11-03 16:47:01 Central processing unit Instruction set architectures Branch predictor Counter Linear feedback shift register CPU cache Hardware performance counter DEC Alpha ARM architecture Computer architecture Computer hardware Computing
53	Shield: Cost-Effective Soft-Error Protection for Register Files Pablo Montesinos, Wei Liu, and Josep Torrellas University of Illinois at Urbana-Champaign {pmontesi, liuwei, torrellas}@cs.uiuc.edu http://iacoma.cs.uiuc.ed Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-10-02 23:53:51 Central processing unit Computer memory Register renaming Register file CPU cache Branch predictor Processor register Parity bit Computer hardware Computer architecture Computing
54	Static Classification for Dynamic Decisions Using Assembler Instrumentation Sylvain Aguirre University of Applied Science EIVD Add to Reading List Source URL: infoscience.epfl.ch Language: English - Date: 2011-07-09 03:33:46 Central processing unit Classes of computers Instruction set architectures Programming language implementation MIPS architecture Branch predictor Instruction set Assembly language Superscalar Computer architecture Computing Computer hardware
55	18-447: Computer Architecture Lecture 12: Control Flow and Exceptions Prof. Onur Mutlu Carnegie Mellon University Spring 2012, [removed] Add to Reading List Source URL: www.ece.cmu.edu Language: English - Date: 2012-02-27 16:19:30 Central processing unit Branch predictor Microarchitecture Superscalar Computer architecture Computer engineering Computer hardware
56	In Proceedings of the 4th International Symposium on High Performance Computing (ISHPC), May 2002, (c) Springer-Verlag. High Performance and Energy Efficient Serial Prefetch Architecture Glenn Reinman Brad Caldery Add to Reading List Source URL: cseweb.ucsd.edu Language: English - Date: 2002-06-24 03:41:14 Cache Computing Computer memory CPU cache Instruction prefetch Branch predictor Alpha 21264 Microarchitecture Pentium Pro Computer hardware Computer architecture Central processing unit
57	Speculative Updates of Local and Global Branch History: A Quantitative Analysis Kevin Skadron SKADRON @ CS . VIRGINIA . EDU Add to Reading List Source URL: www.jilp.org Language: English - Date: 2003-06-05 15:33:55 Central processing unit Instruction set architectures Branch predictor Alpha 21264 CPU cache Out-of-order execution Register renaming Microarchitecture DEC Alpha Computer architecture Computer engineering Computer hardware
58	Improving Application Performance by Dynamically Trading Frequency for Complexity in a GALS Microprocessor∗ Greg Semeraro, David H. Albonesi, Steven Dropsho, Grigorios Magklis, and Michael L. Scott URCS Technical Repor Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2004-02-12 17:49:46 Cache Computing CPU cache Computer memory Microprocessors Alpha 21264 Microarchitecture Branch predictor R8000 Computer hardware Computer architecture Central processing unit
59	Previous chapter 19 pentium: not the same old song Add to Reading List Source URL: downloads.gamedev.net Language: English - Date: 2011-08-09 01:03:16 Instruction set architectures Pentium Pro CPU cache X86 CPUID Pentium Branch predictor Superscalar Intel Core Computer architecture Computing Computer hardware
60	The Energy Impact of Aggressive Loop Fusion YongKang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, and David H. Albonesi Departments of Electrical and Computer Engineering and of Computer Science University of Roc Add to Reading List Source URL: www.cs.rochester.edu Language: English - Date: 2003-12-11 10:02:03 Computer architecture Central processing unit Cache CPU cache Computer memory Parallel computing Loop optimization Software pipelining Branch predictor Computing Compiler optimizations Software engineering

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